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quad, 1 6 - bit, 125 msps , serial lvds 1.8 v analog - to - digital converter data sheet ad9653 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by ana log devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent right s of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.46 1.3113 ? 2012 analog devices, inc. all rights reserved. features 1.8 v supply operation low p ower: 16 4 mw per channel at 125 msps snr = 76.5 db fs at 70 mhz ( 2.0 v p - p input span ) snr = 77.5 db fs at 70 mhz ( 2.6 v p - p input span ) sfdr = 90 dbc (to nyquist , 2.0 v p - p input span ) dnl = 0.7 lsb; inl = 3 .5 lsb ( 2.0 v p - p input span ) serial lvds (ansi - 644, default) and l ow power, reduced range option (similar to ieee 1596.3) 650 mhz full power analog bandwidth 2 v p - p input voltage range (supports up to 2. 6 v p - p) serial port control full chip and individual channel power - down modes flexible bit orientation built - in and custom digital test pattern generation multichip sync and clock divider programmable output clock and data alignment standby mode applications medical ultrasound and mri high s peed i maging quadrature radio receivers diversity radio receivers test equipment general description the ad9653 is a quad, 1 6 - bit, 125 msps analog - to - digital con - verter (adc) with an on - chip sample - and - hold circuit designed for low cost, low power, small size, and ease of use. the product operates at a conversion rate of up to 125 msps and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical. the adc requires a single 1.8 v power supply and lvpecl - / cmos - /lvds - compatible sample rate clock for full performance operation. no external reference or driver components are required for many applications. the adc automatically multiplies the sample rate clock for the appropriate lvds serial data rate. a data clock output (dco) for capturing data on the output and a frame clock output (fco) for signaling a new output byte are provided. individual - channel power - down is supported and typicall y consumes less than 2 mw when all channels are disabled. the adc contains several features designed to maximize flexibility and minimize system cost, such functional block dia gram figure 1. as programmable output clock and da ta alignment and digital test pattern generation. the available digital test patterns include built - in deterministic and pseudorandom patterns, along with custom user - defined test patterns entered via the serial port interface (spi). the ad9653 is available in a rohs - compliant, 48 - lead lfcsp. it is specified over the industrial temperature range of ? 40 c to + 85 c. this product is protected by a u.s. patent. product highlights 1. small footprint. four adcs are contained in a small, space - saving package. 2. low power of 16 4 mw/channel at 125 msps with scalable power options . 3. pin compatible to the ad9253 14 - bit quad and the ad9633 12 - bit q uad adc. 4. ease of use. a data clock output (dco) operates at frequencies of up to 500 mhz and supports double data rate (ddr) ope ration. 5. user flexibility. the spi control offers a wide range of flexible features to meet specific system requirements. ad9653 avdd pdwn drvdd r e f select v i n?a v i n+a v i n?b v i n+b v i n?d v i n+d v i n?c v i n+c sense agnd sync vcm vref d0?a d0+a d0?b d0+b d1?b d1+b d1?c d1+c d0?c d0+c d1?d d1+d dco? dco+ d0?d d0+d fco? fco+ d1?a d1+a c l k+ c l k? c s b sdio/olm sclk/dtp rbias pipeline adc pipeline adc pipeline adc seria l l vds digi t al serializer digi t al serializer digi t al serializer digi t al serializer clock management seria l port inter f ace seria l l vds seria l l vds seria l l vds seria l l vds seria l l vds seria l l vds seria l l vds pipeline adc 16 16 16 16 1v 10538-001
ad9653 data sheet rev. 0 | page 2 of 40 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 dc specifications ......................................................................... 3 ac specifications .......................................................................... 5 digital specifications ................................................................... 7 switching specifications .............................................................. 8 timing specifications .................................................................. 9 absolute maximum ratings .......................................................... 11 thermal resistance .................................................................... 11 esd caution ................................................................................ 11 pin configuration and function descriptions ........................... 12 typical performance characteristics ........................................... 14 v ref = 1.0 v ................................................................................. 14 v ref = 1.3 v ................................................................................. 17 equivalent circuits ......................................................................... 21 theory of operation ...................................................................... 22 analog input considerations .................................................... 22 voltage reference ....................................................................... 23 clock input considerations ...................................................... 25 power dissipation and power - down mo de ........................... 27 digital outputs and timing ..................................................... 27 output test modes ..................................................................... 30 serial por t interface (spi) .............................................................. 31 configuration using the spi ..................................................... 31 hardware interface ..................................................................... 32 configuration without the spi ................................................ 32 spi accessible features .............................................................. 32 memory map .................................................................................. 33 reading the memory map register table ............................... 33 memory map register table ..................................................... 34 memory map register descriptions ........................................ 37 applications information .............................................................. 39 design guidelines ...................................................................... 39 power and ground recommendat ions ................................... 39 exposed pad thermal heat slug recommendations ............ 39 vcm ............................................................................................. 39 ref erence decoupling ................................................................ 39 spi port ........................................................................................ 39 crosstalk performance .............................................................. 39 outline d imensions ....................................................................... 40 ordering guide .......................................................................... 40 revision history 5 /12 revision 0: initial version
data sheet ad9653 rev. 0 | page 3 of 40 specifications dc s pecifications avdd = 1.8 v, drvdd = 1.8 v, 2 .0 v p - p full - scale differential input at ? 1.0 dbfs ; v ref = 1.0 v, dcs off, unless otherwise noted. table 1 . parameter 1 temperature min typ max unit resolution 1 6 bits accuracy no missing codes full guaranteed offset error full ? 0.49 ? 0.3 0.17 % fsr offset matching full ? 0.14 + 0.2 0.39 % fsr gain error full ? 12.3 ? 5 2.37 % fsr gain matching full 1.0 1.1 5.8 % fsr differential nonlinearity (dnl) full ? 0.77 0 . 95 lsb 25 c 0.7 lsb integral nonlinearity (inl) full ? 7.26 8.1 8 lsb 25 c 3 . 5 lsb temperature drift offset error full 3.5 ppm/ c internal voltage reference output voltage (1 .0 v mode) full 0.98 1.0 1.0 1 v load regulation at 1.0 ma (v ref = 1 .0 v) full 2 mv input resistance 25 c 7.5 k input - referred noise v ref = 1.0 v 25 c 2.7 lsb rms analog inputs differential input voltage (v ref = 1 .0 v) full 2 v p -p common - mode voltage full 0.9 v common - mode range 25 c 0.5 1.3 v differential input resistance 25 c 2.6 k different ial input capacitance 25 c 7 pf power supply avdd full 1.7 1.8 1.9 v drvdd full 1.7 1.8 1.9 v i avdd 2 full 305 330 ma i drvdd (ansi - 644 mode) 2 full 60 64 ma i drvdd (reduced range mode) 2 25 c 45 ma total power consumption dc input full 607 649 mw sine wave input (four channels including output drivers , ansi - 644 mode) full 657 708 mw sine wave input (four channels including output drivers , red uced range mode) 25 c 630 mw power - down 25 c 2 mw standby 3 full 356 392 mw 1 see the an - 835 application note , understanding high speed adc testing and evaluation , for definitions and for details on how these tes ts were completed. 2 measured with a low input frequency, full - scale sine wave on all four channels. 3 can be controlled via the spi.
ad9653 data sheet rev. 0 | page 4 of 40 a vdd = 1.8 v, drvdd = 1.8 v, 2. 6 v p - p full - scale differential input at ? 1.0 dbfs; v ref = 1.3 v; 0 c to 85 c, dcs off, unless otherwise noted. table 2 . parameter 1 temperature min typ max unit resolution 16 bits accuracy no missing codes 25 c guaranteed offset error 25 c ? 0.3 % fsr offset matching 25 c + 0.2 % fsr gain error 25 c ? 5 % fsr gain matching 25 c 1.1 % fsr diffe rential nonlinearity (dnl) 25 c 0. 8 lsb integral nonlinearity (inl) 25 c 5 . 0 lsb temperature drift offset error 25 c 3.5 ppm/ c internal voltage reference output voltage (1 .3 v programmable mode) 25 c 1. 3 v load regulation at 1.0 ma (v ref = 1 .3 v) 25 c 6.5 mv input resistance 25 c 7.5 k input - referred noise v ref = 1. 3 v 25 c 2.1 lsb rms analog inputs differential input voltage (v ref = 1 .3 v) 25 c 2 . 6 v p -p common - mode voltage 25 c 0.9 v common - mode range 25 c 0.6 1.3 v differential input resistance 25 c 2.6 k differential input capacitance 25 c 7 pf power supply avdd 25 c 1.8 v drvdd 25 c 1.8 v i avdd 2 25 c 314 ma i drvdd (ansi - 644 mode) 2 25 c 60 ma i drvdd (reduced range mode) 2 25 c 45 ma total power consumption dc input 25 c 614 mw sine wave input (four channels including output drivers , ansi - 644 mode) 25 c 673 mw sine wave input (four channels including output drivers , reduced range mo de) 25 c 646 mw power - down 25 c 2 mw standby 3 25 c 371 mw 1 see the an - 835 application note , understanding high speed adc testing and evaluation , for definitions and for details on how these tests were completed. 2 measured with a low input frequency, full - scale sine wave on all four channels. 3 can be controlled via the spi.
data sheet ad9653 rev. 0 | page 5 of 40 ac specifications avdd = 1.8 v, drvdd = 1.8 v, 2 .0 v p - p full - scale differential input at ? 1.0 dbfs; v ref = 1.0 v , dcs off , unless otherwise noted. table 3 . para meter 1 temperature min typ max unit signal -to - noise ratio (snr) f in = 9.7 mhz 25 c 78 dbfs f in = 15 mhz 25 c 77.8 dbfs f in = 70 mhz full 75.5 76.5 dbfs f in = 1 28 mhz 25 c 73.9 dbfs f in = 200 mhz 25 c 71.5 dbfs signal -to - noise - and - disto rtion ratio (sinad) f in = 9.7 mhz 25 c 78 dbfs f in = 15 mhz 25 c 77.7 dbfs f in = 70 mhz full 74.6 76.1 dbfs f in = 1 28 mhz 25 c 73.6 dbfs f in = 200 mhz 25 c 70.3 dbfs effective number of bits (enob) f in = 9.7 mhz 25 c 12.7 bits f in = 15 mhz 25 c 12.6 bits f in = 70 mhz full 12.1 12.4 bits f in = 1 28 mhz 25 c 11.9 bits f in = 200 mhz 25 c 11.4 bits spurious - free dynamic range (sfdr) f in = 9.7 mhz 25 c 96 dbc f in = 15 mhz 25 c 93 dbc f in = 70 mhz full 78 89 dbc f in = 1 28 mhz 25 c 87 dbc f in = 200 mhz 25 c 77 dbc worst harmonic (second or third) f in = 9.7 mhz 25 c ? 9 8 dbc f in = 15 mhz 25 c ? 9 3 dbc f in = 70 mhz full ? 78 ? 89 dbc f in = 1 28 mhz 25 c ? 87 dbc f in = 200 mhz 25 c ? 77 dbc worst other harmonic or spur f in = 9.7 mhz 25 c ? 9 6 dbc f in = 15 mhz 25 c ? 98 dbc f in = 70 mhz full ? 85 ? 9 4 dbc f in = 1 28 mhz 25 c ? 89 dbc f in = 200 mhz 25 c ? 8 3 dbc two - tone intermodulation distortion (imd) ain 1 and ain 2 = ? 7.0 dbfs f in1 = 70.5 mhz, f in2 = 72.5 mhz 25 c ? 90 dbc crosstalk 2 25 c 91 db crosstalk (overrange condition) 3 25 c 8 7 db power supply rejection ratio (psrr) 4 avdd 25 c 31 db drvdd 25 c 79 db analog input bandwidth, full power 25 c 650 mhz 1 see the an - 835 application note , understanding high speed adc testing and evaluation , for definitions and for details on how these tests were completed. 2 crosstalk is measured at 70 mhz with ?1.0 dbfs analog input on one channel and no input on the adjacent channel. 3 overrange condition is defined as the input being 3 db above full scale. 4 psrr is measured by injecting a sinusoidal signal at 10 mhz to the power supply pin and measuring the output spur on the fft. psrr is calculated as the ratio of the amplitudes of t he spur voltage over the pin voltage, expressed in decibels.
ad9653 data sheet rev. 0 | page 6 of 40 avdd = 1.8 v, drvdd = 1.8 v, 2.6 v p - p full - scale differential input at ? 1.0 dbfs; v ref = 1.3 v; 0 c to 85 c , dcs off , u nless otherwise noted. table 4 . parameter 1 temperature min typ max unit signal -to - noise ratio (snr) f in = 9.7 mhz 25 c 80 dbfs f in = 15 mhz 25 c 79.4 dbfs f in = 70 mhz 25 c 77.5 dbfs f in = 1 28 mhz 25 c 74.4 dbfs f in = 200 mhz 25 c 71.7 dbfs signal -to - noise - and - distortion ratio (sinad) f in = 9.7 mhz 25 c 79.8 dbfs f in = 15 mhz 25 c 79.2 dbfs f in = 70 mhz 25 c 76.1 dbfs f in = 1 28 mhz 25 c 74 dbfs f in = 200 mhz 25 c 69.9 dbfs effective number o f bits (enob) f in = 9.7 mhz 25 c 13 bits f in = 15 mhz 25 c 12.9 bits f in = 70 mhz 25 c 12.3 bits f in = 1 28 mhz 25 c 12 bits f in = 200 mhz 25 c 11.3 bits spurious - free dynamic range (sfdr) f in = 9.7 mhz 25 c 9 4 dbc f in = 15 mhz 25 c 9 4 dbc f in = 70 mhz 25 c 82 dbc f in = 1 28 mhz 25 c 86 dbc f in = 200 mhz 25 c 75 dbc worst harmonic (second or third) f in = 9.7 mhz 25 c ? 94 dbc f in = 15 mhz 25 c ? 94 dbc f in = 70 mhz 25 c ? 82 dbc f in = 1 28 mhz 25 c ? 87 dbc f in = 200 mhz 25 c ? 75 dbc worst other harmonic or spur f in = 9.7 mhz 25 c ? 100 dbc f in = 15 mhz 25 c ? 99 dbc f in = 70 mhz 25 c ? 9 6 dbc f in = 1 28 mhz 25 c ? 8 6 dbc f in = 200 mhz 25 c ? 8 4 dbc two - tone intermodulation distortion (imd) ain 1 and ain 2 = ? 7.0 dbfs f in1 = 70.5 mhz, f in2 = 72.5 mhz 25 c ? 90 dbc crosstalk 2 25 c 9 1 db crosstalk (overrange condition) 3 25 c 8 7 db powe r supply rejection ratio (psrr) 4 avdd 25 c 31 db drvdd 25 c 79 db analog input bandwidth, full power 25 c 650 mhz 1 see the an - 835 application note , understanding high speed adc testing and evaluation , for definitions and for details on how these tests were completed. 2 crosstalk is measured at 70 mhz with ?1.0 dbfs analog input on one channel and no input on the adjacent channel. 3 overrange condition is defined as the input being 3 db above full scal e. 4 psrr is measured by injecting a sinusoidal signal at 10 mhz to the power supply pin and measuring the output spur on the fft. psrr is calculated as the ratio of the amplitudes of the spur voltage over the pin voltage, expressed in decibels.
data sheet ad9653 rev. 0 | page 7 of 40 digital specificatio ns av dd = 1.8 v, drvdd = 1.8 v, unless otherwise noted. table 5 . parameter 1 temp min typ max unit clock inputs (clk+, clk?) logic compliance cmos/lvds/lvpecl differential input voltage 2 full 0.2 3.6 v p -p input voltage range full agnd ? 0. 2 avdd + 0.2 v input common - mode voltage full 0.9 v input resistance (differential) 25 c 15 k i nput capacitance 25 c 4 pf logic inputs (pdwn, sync, sclk) logic 1 voltage full 1.2 avdd + 0. 2 v logic 0 voltage full 0 0.8 v input resistance 25 c 30 k input capacitance 25 c 2 pf logic input (csb) logic 1 voltage full 1.2 avdd + 0.2 v logic 0 voltage full 0 0.8 v input resistance 25 c 26 k input capacitance 25 c 2 pf logic input (sdio) logic 1 voltage full 1.2 avdd + 0. 2 v logic 0 voltage full 0 0.8 v input resistance 25 c 26 k input capacitance 25 c 5 pf logic output (sdio) 3 logic 1 voltage (i oh = 800 a) full 1.79 v logic 0 voltage (i ol = 50 a) full 0.05 v digital outputs (d 0 x, d 1 x), ansi - 644 logic compliance lvds differential output voltage (v od ) full 290 345 400 mv output offset voltage (v os ) full 1.15 1.25 1.35 v output coding (default) two s c omplement digital outputs (d0x, d1x), low power, reduced signal option logic compliance lvds differential output voltage (v od ) full 160 200 230 mv output offset volt age (v os ) full 1.15 1.25 1.35 v output coding (default) twos c omplement 1 see the an - 835 application note , understanding high speed adc testing and evaluation , for definitions and for details on how these tests were completed. 2 this is specified for lvds and lvpecl only. 3 this is specified for 13 sdio/olm pins sharing the same connection.
ad9653 data sheet rev. 0 | page 8 of 40 switching specificat ions av dd = 1.8 v, drvdd = 1.8 v, unless otherwise noted. table 6 . parameter 1 , 2 temp min typ max unit clock 3 input clock rate full 2 0 1000 mhz conversion rate full 2 0 125 msps clock pulse width high (t eh ) full 4.00 ns clock pulse width low (t el ) full 4.00 ns output parameters 3 propagation delay (t pd ) full 2.3 ns r ise time (t r ) (20% to 80% ) full 300 ps fall time (t f ) ( 20% to 80% ) full 300 ps fco propagation delay (t fco ) full 1.5 2.3 3.1 ns dco propagation delay (t cpd ) 4 full t fco + (t sample /1 6 ) ns dco to data delay (t data ) 4 full (t sample /1 6 ) ? 300 (t sample /1 6 ) (t sample /1 6 ) + 300 ps dco to fco delay (t frame ) 4 full (t sample /1 6 ) ? 300 (t sample /1 6 ) (t sample /1 6 ) + 300 ps lane delay (t ld ) 90 ps data to data skew (t data - max ? t data - min ) full 50 200 ps wake - up time (standby) 25c 250 ns wake - up time (power - down) 5 25c 375 s pipeline latency full 16 clock cycles aperture aperture delay (t a ) 25c 1 ns aperture uncertainty (jitter , t j ) 25c 1 35 f s rms out -of - range recovery time 25c 1 c lock cycles 1 see the an - 835 application note , understanding high speed adc testing and evaluation , for definitions and for details on how these tests were completed. 2 meas ured on standard fr - 4 material. 3 can be adjusted via the spi. the conversion rate is the clock rate after the divider. 4 t sample /16 is based on the number of bits in two lvds data lanes. t sample = 1/f s . 5 wake - up time is defined as the time required to return to normal operation from power - down mode.
data sheet ad9653 rev. 0 | page 9 of 40 timing specification s table 7 . parameter description limit unit sync timing requirements t ssync sync to rising edge of clk+ setup time 0.24 ns typ t hsync sync to rising edge of clk+ hold time 0.40 ns typ spi timing requirements see figure 75 t ds setup time between the data and the rising edge of sclk 2 ns min t dh hold time between the data and the rising edge of sclk 2 ns min t clk period of the sclk 40 ns min t s setup time between csb and sclk 2 ns min t h hold time between csb and sclk 2 ns min t high sclk pulse width high 10 ns min t low sclk pulse width low 10 ns min t en_sdio time required for the sdio pin to switch from an input to an output relative to the sclk falling edge (not shown in figure 75) 10 ns min t dis_sdio time required for the sdio pin to switch from an output to an input relative to the sclk rising edge (not shown in figure 75) 10 ns min timing diagrams refer to the memory map register descriptions section and tale 23 fo r spi register settings figure 2 . 16 - bit ddr/sdr, two - lane, 1 frame mode (default) d0? a d0+ a d1? a d1+ a fco? bytewise mode fco+ d0? a d0+ a d1? a d1+ a fco? dco dco+ clk+ vinx clk? dco? fco+ bitwise mode sdr ddr 10538-002 msb n ? 17 d14 n ? 17 d13 n ? 17 d12 n ? 17 d11 n ? 17 d10 n ? 17 d09 n ? 17 d08 n ? 17 msb n ? 16 d14 n ? 16 d13 n ? 16 d12 n ? 16 d11 n ? 16 d10 n ? 16 d09 n ? 16 d08 n ? 16 d07 n ? 17 d06 n ? 17 d05 n ? 17 d04 n ? 17 d03 n ? 17 d02 n ? 17 d01 n ? 17 lsb n ? 17 d07 n ? 16 d06 n ? 16 d05 n ? 16 d04 n ? 16 d03 n ? 16 d02 n ? 16 d01 n ? 16 lsb n ? 16 msb n ? 17 d13 n ? 17 d11 n ? 17 d09 n ? 17 d07 n ? 17 d05 n ? 17 d03 n ? 17 d01 n ? 17 msb n ? 16 d13 n ? 16 d11 n ? 16 d09 n ? 16 d07 n ? 16 d05 n ? 16 d03 n ? 16 d01 n ? 16 d14 n ? 17 d12 n ? 17 d10 n ? 17 d08 n ? 17 d06 n ? 17 d04 n ? 17 d02 n ? 17 lsb n ? 17 d14 n ? 16 d12 n ? 16 d10 n ? 16 d08 n ? 16 d06 n ? 16 d04 n ? 16 d02 n ? 16 lsb n ? 16 t a t data t ld t eh t fco t frame t pd t cpd t el n ? 1 n n + 1
ad9653 data sheet rev. 0 | page 10 of 40 figure 3 . 16 - bit ddr/sdr , two - lane , 2 frame mode figure 4 . wordw ise ddr, one - lane, 1 fr ame, 16 - bit output mode figure 5 . sync input timing requirements d0? a d0+ a d1? a d1+ a fco? bytewise mode fco+ d0? a d0+ a d1? a d1+ a fco? dco dco+ clk+ vinx clk? dco? fco+ bitwise mode sdr ddr msb n ? 17 d14 n ? 17 d13 n ? 17 d12 n ? 17 d11 n ? 17 d10 n ? 17 d09 n ? 17 d08 n ? 17 msb n ? 16 d14 n ? 16 d13 n ? 16 d12 n ? 16 d11 n ? 16 d10 n ? 16 d09 n ? 16 d08 n ? 16 d07 n ? 17 d06 n ? 17 d05 n ? 17 d04 n ? 17 d03 n ? 17 d02 n ? 17 d01 n ? 17 lsb n ? 17 d07 n ? 16 d06 n ? 16 d05 n ? 16 d04 n ? 16 d03 n ? 16 d02 n ? 16 d01 n ? 16 lsb n ? 16 msb n ? 17 d13 n ? 17 d11 n ? 17 d09 n ? 17 d07 n ? 17 d05 n ? 17 d03 n ? 17 d01 n ? 17 msb n ? 16 d13 n ? 16 d11 n ? 16 d09 n ? 16 d07 n ? 16 d05 n ? 16 d03 n ? 16 d01 n ? 16 d14 n ? 17 d12 n ? 17 d10 n ? 17 d08 n ? 17 d06 n ? 17 d04 n ? 17 d02 n ? 17 lsb n ? 17 d14 n ? 16 d12 n ? 16 d10 n ? 16 d08 n ? 16 d06 n ? 16 d04 n ? 16 d02 n ? 16 lsb n ? 16 t a t data t ld t eh t fco t frame t pd t cpd t el n ? 1 n + 1 n 10538-003 d0?x d0+x fco? dco+ clk+ vinx clk? dco? fco+ d14 n ? 17 msb n ? 17 d13 n ? 17 d12 n ? 17 d11 n ? 17 d10 n ? 17 d9 n ? 17 d8 n ? 17 d7 n ? 17 d6 n ? 17 d5 n ? 17 d4 n ? 17 d3 n ? 17 d2 n ? 17 d1 n ? 17 lsb n ? 17 msb n ? 16 d14 n ? 16 d13 n ? 16 t a t data t eh t fco t frame t pd t cpd t el n ? 1 n 10538-004 sync clk+ t hsync t ssync 10538-005
data sheet ad9653 rev. 0 | page 11 of 40 absolute maximum rat ings table 8 . parameter rating electrical avdd to agnd ? 0.3 v to + 2.0 v drvdd to agnd ? 0.3 v to + 2.0 v digital ou tputs (d 0 x, d 1 x, dco+, dco?, fco+, fco?) to agnd ? 0.3 v to + 2.0 v clk+, clk? to agnd ? 0.3 v to + 2.0 v vin +x, vin ? x to agnd ? 0.3 v to + 2.0 v sclk /dtp , sdio /olm , csb to agnd ? 0.3 v to + 2.0 v sync, pdwn to agnd ? 0.3 v to + 2.0 v rbias to agnd ? 0.3 v to + 2.0 v vref, sense to agnd ? 0.3 v to + 2.0 v environmental operating temperature range (ambient , v ref = 1.0 v ) ? 40 c to +85c operating temperature range (ambient , v ref = 1.3 v ) 0 c to 85c maximum junction temperature 150c lead temperatur e (soldering, 10 sec) 300c storage temperature range (ambient) ? 65c to +150 c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at the se or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance table 9 . thermal resistance package type air flow velocity (m/sec) ja 1 jb jc unit 48 - lead lfcsp 0.0 23.7 7.8 7.1 c/w 7 mm 7 mm 1.0 20.0 n/a n/a c/w (cp -48 -13) 2.5 18.7 n/a n/a c/w 1 ja for a 4 - layer pcb with solid ground plane (simulated). exposed pad soldered to pcb. esd caution
ad9653 data sheet rev. 0 | page 12 of 40 pin configuration a nd function descript ions figure 6 . 48 - lead lfcsp pin configuration, top view table 10 . pin function descriptions pin no. mnemonic description 0 agnd , exposed pad analog ground , exposed pad. the exposed thermal pad on the bottom of the package provides the analog ground for the part. this exposed pad must be connected to ground for proper operation. 1 vin+d adc d analog input true . 2 vin ? d adc d analog input complement . 3, 4, 7, 34, 39, 45, 46 avdd 1.8 v analog supply pins . 5, 6 clk ? , clk+ differential encode clock. pecl, lvds, or 1.8 v cmos inputs . 8, 29 drvdd digital output driver supply . 9, 10 d1 ? d, d 1 +d channel d digital outputs . 11, 12 d0 ? d, d 0 +d channel d digital outputs . 13, 14 d1 ? c, d 1 +c channel c digital outputs . 15, 16 d0 ? c, d 0 +c channel c digital outputs . 17, 18 dco ? , dco+ data clock outputs . 19, 20 fco ? , fco+ frame clock outputs . 21, 22 d1 ? b, d 1 +b channel b digital ou tputs . 23, 24 d0 ? b, d 0 +b channel b digital outputs . 25, 26 d1 ? a, d 1 +a channel a digital outputs . 27, 28 d0 ? a, d 0 +a channel a digital outputs . 30 sclk/dtp spi clock input/digital test pattern . 31 sdio/o l m spi data input and output bidirectional spi dat a /output lane mode . 32 csb spi chip select bar. active low enable; 30 k internal pull - up. 33 pdwn digital input , 30 k internal pull - down . pdwn high = power - down device . pdwn low = run device, normal operation . 35 vin?a adc a analog input complement . 36 vin + a adc a analog input true . 37 vin+b adc b analog input true . 38 vin ? b adc b analog input complement . 40 rbias sets analog current bias. connect to 10 k ( 1% tolerance) resistor to ground. 41 sense reference mode selection . 42 vref voltage refer ence input and output . 43 vcm analog input common - mode voltage . 1 2 3 vin+ a vin? a a vdd 4 pdwn 5 csb 6 sdio/olm 7 sclk/dt p 24 d0+b 23 d0?b 22 d1+b 21 d1?b 20 fco+ 19 fco? 18 dco+ 17 dco? 16 d0+c 15 d0?c 14 d1+c 13 d1?c 44 sync 45 a vdd 46 a vdd 47 vin?c 48 vin+c 43 vcm 42 vref 41 sense 40 rbias 39 a vdd 38 vin?b 37 vin+b 25 d0+d 26 d0?d 27 d1+d 28 d1?d 29 d r vdd 30 a vdd 31 clk+ 32 clk? 33 a vdd 34 a vdd 35 vin?d 36 vin+d 8 dr vdd 9 d0+ a 10 d0? a 1 1 d1+ a 12 d1? a ad9653 t op view (not to scale) notes 1. the exposed thermal pad on the bottom of the package provides the analog ground for the part. this exposed pad must be connected to ground for proper operation. 10538-006
data sheet ad9653 rev. 0 | page 13 of 40 pin no. mnemonic description 44 sync digital input. sync input to clock divider. 47 vin?c adc c analog input complement . 48 vin + c adc c analog input true .
ad9653 data sheet rev. 0 | page 14 of 40 typical performance characteristics v ref = 1.0 v figur e 7 . single- tone 16k fft with f in = 9.7 mhz, f sample = 125 msps , v ref = 1.0 v figure 8 . single- tone 16k fft with f in = 1 5 mhz, f sample = 125 msps , v ref = 1.0 v figure 9. s ingle - tone 16k fft with f in = 64 mhz, f sample = 125 msps , v ref = 1.0 v figure 10 . single - tone 16k fft with f in = 70 mhz, f sample = 125 msps , v ref = 1.0 v figure 11 . single - tone 16k fft with f in = 128 mhz, f sample = 125 msps , v ref = 1.0 v figure 12 . single - tone 16k fft with f in = 200.5 mhz at f sample = 1 25 msps , v ref = 1.0 v 0 ?30 ?60 ?15 ?45 ?75 ?90 ?105 ?120 ?135 0 12 + 2 3 4 5 6 18 6 24 30 36 42 48 60 54 amplitude (dbfs) frequency (mhz) 125msps 9.7mhz at ?1dbfs snr = 77.1db (78.1dbfs) sfdr = 96.8dbc 10538-007 + 2 3 4 0 ?30 ?60 ?15 ?45 ?75 ?90 ?105 ?120 ?135 0 12 18 6 24 30 36 42 48 60 54 amplitude (dbfs) frequency (mhz) 125msps 15mhz at ?1dbfs snr = 76.8db (77.8dbfs) sfdr = 95.2dbc 5 6 10538-008 0 ?30 ?60 ?15 ?45 ?75 ?90 ?105 ?120 ?135 0 12 18 6 24 30 36 42 48 60 54 amplitude (dbfs) frequency (mhz) + 2 3 4 5 6 125msps 64mhz at ?1dbfs snr = 75.7db (76.7dbfs) sfdr = 87.2dbc 10538-009 0 ?30 ?60 ?15 ?45 ?75 ?90 ?105 ?120 ?135 0 12 + 2 3 4 5 6 18 6 24 30 36 42 48 60 54 amplitude (dbfs) frequency (mhz) 125msps 70mhz at ?1dbfs snr = 75.6db (76.6dbfs) sfdr = 85.5dbc 10538-010 0 ?30 ?60 ?15 ?45 ?75 ?90 ?105 ?120 ?135 0 12 + 2 3 4 5 6 18 6 24 30 36 42 48 60 54 amplitude (dbfs) frequency (mhz) 125msps 128mhz at ?1dbfs snr = 73.2db (74.2dbfs) sfdr = 86.6dbc 10538-0 1 1 0 ?30 ?60 ?15 ?45 ?75 ?90 ?105 ?120 ?135 0 12 + 2 3 4 5 6 18 6 24 30 36 42 48 60 54 amplitude (dbfs) frequency (mhz) 125msps 200.5mhz at ?1dbfs snr = 70.7db (71.7dbfs) sfdr = 76.6dbc 10538-012
data sheet ad9653 rev. 0 | page 15 of 40 figure 13 . snr/sfdr vs. input amplitude (ain) , f in = 9.7 mhz, f sample = 125 msps , v ref = 1.0 v figure 14 . two - tone 16k fft with f in1 = 70.5 mhz and f in2 = 72.5 mhz, f sample = 125 msps , v ref = 1.0 v figure 15 . two - tone sfdr/imd3 vs. input amplitude (ain) with f in1 = 70.5 mhz and f in2 = 72.5 mhz, f sample = 125 msps , v ref = 1.0 v figure 16 . snr/sfdr vs. f in , f sample = 125 msps , cl oc k divider = 8 , v ref = 1.0 v figure 17 . snr/sfdr vs. temperature, f in = 9.7 mhz, f sample = 125 msps , v ref = 1.0 v figure 18 . inl, f in = 9.7 mhz, f sample = 125 msps , v ref = 1.0 v ?20 0 20 40 60 80 100 120 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 snr/sfdr (dbfs/dbc) input amplitude (dbfs) 10538-013 sfdrfs snrfs sfdr snr 0 ?30 ?60 ?15 ?45 ?75 ?90 ?105 ?120 ?135 0 12 f2 ? f1 f1 + f2 + 2f2 + f1 2f1 + f2 f2 ? f1 2f1 ? f2 18 6 24 30 36 42 48 6054 amplitude (dbfs) frequency (mhz) 10538-014 i md3 (d bc ) ?120 ?100 ?80 ?60 ?40 ?20 0 ?90 ?70 ?50 ?30 ?10 sfdr/imd3(dbc/dbfs) input amplitude (dbfs) i md3 (d bfs ) sf dr (d bfs ) sf dr (d bc ) 10538-015 0 20 40 60 80 100 120 0 20 40 60 80 100 120 140 160 180 200 snr/sfdr (dbfs/dbc) input frequenc y (mhz) snr (d bfs ) sf dr (d bc ) 10538-016 70 75 80 85 90 95 100 ?40 ?20 0 20 40 60 80 snr/sfdr(dbfs/dbc) tempera ture (c) sf dr (d bc ) snr (d bfs ) 10538-017 0 inl (lsb) output code ?4.5 ?3.0 ?1.5 0 1.5 3.0 4.5 6000 12000 18000 24000 30000 36000 42000 48000 54000 60000 10538-018
ad9653 data sheet rev. 0 | page 16 of 40 figure 19 . dnl, f in = 9.7 mhz, f sample = 125 msps , v ref = 1.0 v figure 20 . input - referred noise histogram, f sample = 125 msps , v ref = 1.0 v figure 21 . psrr vs. frequency, f sample = 125 msps , v ref = 1.0 v figure 22 . snr/sfdr vs. sample rate , f in = 9.7 mhz , v ref = 1.0 v figure 23 . snr/sfdr vs. sample rate , f in = 64 mhz , clock divider = 4 , v ref = 1.0 v 0 dnl (lsb) output code ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.8 0.6 6000 12000 18000 24000 30000 36000 42000 48000 54000 60000 10538-019 0 20000 40000 60000 80000 100000 120000 140000 160000 n ? 12 n ? 1 1 n ? 10 n ? 9 n ? 8 n ? 7 n ? 6 n ? 5 n ? 4 n ? 3 n ? 2 n ? 1 n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 n + 8 n + 9 n + 10 n + 1 1 n + 12 n + 13 number of hits code 10538-020 2.7 lsb rms 0 10 20 30 40 50 60 70 80 90 100 1 10 70 psrr (db) frequenc y (mhz) dr v dd av dd 10538-021 0 20 40 60 80 100 20 40 60 80 100 120 snr/sfdr (dbfs/dbc) sample r a te (msps) 10538-022 sf dr ( d bc ) s n r ( d bfs ) 0 20 40 60 80 100 20 40 60 80 100 120 snr/sfdr (dbfs/dbc) sample r a te (msps) 10538-023 s n r ( d bfs ) sf dr ( d bc )
data sheet ad9653 rev. 0 | page 17 of 40 v ref = 1.3 v figure 24 . single - tone 16k fft with f in = 9.7 mhz, f sample = 125 msps , v ref = 1.3 v figur e 25 . single - tone 16k fft with f in = 1 5 mhz, f sample = 125 msps , v ref = 1.3 v figure 26 . single - tone 16k fft with f in = 64 mhz, f sample = 125 msps , v ref = 1.3 v figure 27 . single - tone 16k fft with f in = 7 0 mhz, f sample = 125 msps , v ref = 1.3 v figure 28 . single - tone 16k fft with f in = 128 mhz, f sample = 125 msps , v ref = 1.3 v figure 29 . single - tone 16k fft with f in = 200.5 mhz, f sample = 12 5 msps , v ref = 1.3 v 0 ?30 ?60 ?15 ?45 ?75 ?90 ?105 ?120 ?135 0 12 + 2 3 4 5 6 18 6 24 30 36 42 48 60 54 amplitude (dbfs) frequency (mhz) 125msps 9.7mhz at ?1dbfs snr = 79.1db (80.1dbfs) sfdr = 93.5dbc 10538-024 0 ?30 ?60 ?15 ?45 ?75 ?90 ?105 ?120 ?135 0 12 + 2 3 4 5 6 18 6 24 30 36 42 48 60 54 amplitude (dbfs) frequency (mhz) 125msps 15mhz at ?1dbfs snr = 78.3db (79.3dbfs) sfdr = 94.5dbc 10538-025 0 ?30 ?60 ?15 ?45 ?75 ?90 ?105 ?120 ?135 0 12 + 2 3 4 5 6 18 6 24 30 36 42 48 60 54 amplitude (dbfs) frequency (mhz) 125msps 64mhz at ?1dbfs snr = 76.9db (77.9dbfs) sfdr = 82.6dbc 10538-026 0 ?30 ?60 ?15 ?45 ?75 ?90 ?105 ?120 ?135 0 12 + 2 3 4 5 6 18 6 24 30 36 42 48 60 54 amplitude (dbfs) frequency (mhz) 125msps 70mhz at ?1dbfs snr = 76.7db (77.7dbfs) sfdr = 82.1dbc 10538-027 0 ?30 ?60 ?15 ?45 ?75 ?90 ?105 ?120 ?135 0 12 + 2 3 4 5 6 18 6 24 30 36 42 48 60 54 amplitude (dbfs) frequency (mhz) 125msps 128mhz at ?1dbfs snr = 73.5db (74.5dbfs) sfdr = 86.7dbc 10538-028 0 ?30 ?60 ?15 ?45 ?75 ?90 ?105 ?120 ?135 0 12 + 2 3 4 5 18 6 24 30 36 42 48 60 54 amplitude (dbfs) frequency (mhz) 125msps 200.5mhz at ?1dbfs snr = 71.1db (72.1dbfs) sfdr = 73.7dbc 10538-029 6
ad9653 data sheet rev. 0 | page 18 of 40 figure 30 . single - tone 16k fft with f in = 15 mhz, f sample = 80 msps , v ref = 1.3 v figure 31 . single - tone 16k fft with f in = 64 .5 mhz, f sample = 80 msps , v ref = 1.3 v figure 32 . snr/sfdr vs. input amplitude (ain) , f in = 9.7 mhz, f sample = 125 msps , v ref = 1.3 v figure 33 . two - tone 16k fft with f in1 = 70.5 mhz and f in2 = 72.5 mhz, f sample = 125 msps , v ref = 1.3 v figure 34 . two - tone sfdr/imd3 vs. input amplitude (ain) with f in1 = 70.5 mhz and f in2 = 72.5 mhz, f sample = 125 msps , v ref = 1.3 v figure 35 . snr/sfdr vs. f in , f sample = 125 msps , cl oc k divider = 8 , v ref = 1.3 v 0 ?30 ?60 ?15 ?45 ?75 ?90 ?105 ?120 ?135 8 + 2 3 12 40 16 20 24 28 32 36 40 amplitude (dbfs) frequency (mhz) 80msps 15mhz at ?1dbfs snr = 79.0db (80.0dbfs) sfdr = 90.5dbc 10538-030 6 4 5 0 ?30 ?60 ?15 ?45 ?75 ?90 ?105 ?120 ?135 8 + 2 3 12 40 16 20 24 28 32 36 40 amplitude (dbfs) frequency (mhz) 80msps 15mhz at ?1dbfs snr = 76.7db (77.7dbfs) sfdr = 82.1dbc 10538-031 6 4 5 ?20 0 20 40 60 80 100 120 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 snr/sfdr (dbfs/dbc) input amplitude (dbfs) sfdrfs snrfs sfdr snr 10538-032 0 ?30 ?60 ?15 ?45 ?75 ?90 ?105 ?120 ?135 0 12 f2 ? f1 f1 + f2 + 2f2 + f1 2f1 + f2 2f2 ? f1 2f1 ? f2 18 6 24 30 36 42 48 6054 amplitude (dbfs) frequency (mhz) 10538-033 i md3 (d bc ) ?120 ?100 ?80 ?60 ?40 ?20 0 ?90 ?70 ?50 ?30 ?10 sfdr/imd3 (dbc/dbfs) input amplitude (dbfs) i md3 (d bfs ) sf dr (d bfs ) sf dr (d bc ) 10538-034 0 10 20 30 40 50 60 70 80 90 100 0 20 40 60 80 100 120 140 160 180 200 snr/sfdr (dbfs/dbc) input frequenc y (mhz) sf dr (d bc ) snr (d bfs ) 10538-035
data sheet ad9653 rev. 0 | page 19 of 40 figure 36 . snr/sfdr vs. temperature, f in = 9.7 mhz, f sample = 125 msps , v ref = 1.3 v figure 37 . inl, f in = 9.7 mhz, f sample = 125 msps , v ref = 1.3 v figure 38 . dnl, f in = 9.7 mhz, f sample = 125 msps , v ref = 1.3 v figure 39 . input - referred noise histogram, f sample = 125 msps , v ref = 1.3 v figure 40 . psrr vs. frequency, f sample = 1 25 msps , v ref = 1.3 v figure 41 . snr/sfdr vs. sample rate , f in = 9.7 mhz , v ref = 1.3 v s n r ( d bfs ) sf dr ( d bc ) 78 80 82 84 86 88 90 92 94 0 20 40 60 80 snr/sfdr (dbfs/dbc) temper a ture (c) 10538-036 0 inl (lsb) output code ?4.5 ?3.0 ?1.5 0 1.5 3.0 4.5 6000 12000 18000 24000 30000 36000 42000 48000 54000 60000 10538-037 0 dnl (lsb) output code ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.8 0.6 6000 12000 18000 24000 30000 36000 42000 48000 54000 60000 10538-038 0 20000 40000 60000 80000 100000 120000 140000 160000 180000 200000 n ? 9 n ? 8 n ? 7 n ? 6 n ? 5 n ? 4 n ? 3 n ? 2 n ? 1 n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 n + 8 n + 9 n + 10 number of hits code 10538-039 2.1 lsb rms 0 10 20 30 40 50 60 70 80 90 100 1 10 70 psrr (db) frequenc y (mhz) dr v dd av dd 10538-040 0 20 40 60 80 100 20 40 60 80 100 120 snr/sfdr (dbfs/dbc) sample r a te (msps) sf dr ( d bc ) s n r ( d bfs ) 10538-041
ad9653 data sheet rev. 0 | page 20 of 40 figure 42 . snr/sfdr vs. sample rate , f in = 64 mhz , cl oc k divider = 4 , v ref = 1.3 v 0 20 40 60 80 100 20 40 60 80 100 120 snr/sfdr (dbfs/dbc) sample r a te (msps) s n r ( d bfs ) sf dr ( d bc ) 10538-042
data sheet ad9653 rev. 0 | page 21 of 40 equivalent circuits figure 43 . equivalent analog input circuit figure 44 . equivalent clock input circuit figure 45 . equivalent sdio/olm input circuit figure 46 . equivalent digital output circuit figure 47 . equivalent sclk /dtp , sync , and pdwn input circuit figure 48 . equivalent rbias and vcm circuit figure 49 . equivalen t cs input circuit figure 50 . equivalent vref circuit a vdd vinx 10538-043 clk+ clk? 0.9v 15k? 10? 10? 15k? a vdd a vdd 10538-044 31k? sdio/olm 400? a vdd 10538-045 dr vdd d0?x, d1?x d0+x, d1+x v v v v 10538-046 350? a vdd 30k? sclk/dt p , sync, and pdwn 10538-047 rbias and vcm 375? a vdd 10538-048 csb 350? a vdd 30k? 10538-049 vref a vdd 7.5k? 375? 10538-050
ad9653 data sheet rev. 0 | page 22 of 40 theory of operation the ad9653 is a multistage, pipelined ad c . each stage provides sufficient overlap to correct for flash errors in the preceding stage. the quantized outputs from each stage are combined into a final 1 6 - bit result in the digital correction logic. the serializer transmits this converted data in a 1 6 - bit output. the pipelined architecture permits the first stage to operate with a new input sample while the remaining stages operate with preceding samples. sampling occurs on the rising edge of the clock. each stage of the pipeline, excluding the last, consists of a low resolution flash adc connected to a switched - capacitor dac and an interstage residue amplifier (for example, a multiplying digital - to - analog converter (mdac)). the residue amplifier magnifies the difference between the reconstructed dac o utput and the flash input for the next stage in the pipeline. one bit of redundancy is used in each stage to facilitate digital correction of flash errors. the last stage simply consists of a flash adc. the output staging block aligns the data, corrects er rors, and passes the data to the output buffers. the data is then serialized and aligned to the frame and data clocks. analog input conside rations the analog input to the ad9653 is a differential switched - capacitor circuit designed for processing differential input signals. this circuit can support a wide common - mode range while maintaining excellent performance. by using an input common - mode voltage of midsupply, user s can minimize signal - dependent errors and achieve optimum performance. figure 51 . switched - capacitor input circuit the clock signal alternately switches the input circuit between sample mode and hold mode (see figure 51 ). when the input circuit is switched to sample mode, the signal source must be capable of charging the sample capacitors and settling within one - half of a clock cycle. a small resistor in series with each input can help reduce the peak transient current injected from the output stage of the driving source. in addition, low q inductors or ferrite beads can be placed on each leg of the input to reduce high differential capacitance at the analog inputs and therefore achiev e the maximum bandwidth of the adc. such use of low q inductors or ferrite beads is required when driving the converter front end at high if frequencies. either a differential capacitor or two single - ended capacitors can be placed on the inputs to provide a matching passive network. this ultimately creates a low - pass filter at the input to limit unwanted broadband noise. see the an - 742 application note , the an - 827 appli cation note , and the analog dialogue article transformer - coupled front - end for wideband a/d converters (volume 39, april 2005) for more information . in general, the precise values depend on the application. input common mode the analog inputs of the ad9653 are not internally dc - biased. therefore, in ac - coupled applications, the user must provide this bias externally. setting the device so that v cm = av dd /2 is recommended for optimum performance, but the device can function over a wider range with reasonable performance, as shown in fi gure 52 and figure 53. an on - chip , common - mode voltage reference is included in the design and is available from the vcm pin. the vcm pin must be bypassed to ground by a 0.1 f capacitor, as described in the applications information section. maximum snr performance is achieved by setting the adc to the largest span in a differential configuration. in the case of the ad9653 , the input span is dependent on the reference voltage (see table 11) . figure 52 . snr/sfdr vs. common - mode voltage, f in = 9.7 mhz, f sample = 125 msp s , v ref = 1.0 v s s h c par c sample c sample c par v i n?x h s s h v i n+x h 10538-051 20 30 40 50 60 70 80 90 100 1 10 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 snr/sfdr (dbfs/dbc) common-mode vo lt age (v) sf dr (dbc) s n rf s (dbfs) 10538-052
data sheet ad9653 rev. 0 | page 23 of 40 figure 53 . snr/sfdr vs. common - mode voltage, f in = 9.7 mhz, f sample = 125 msps , v ref = 1.3 v differential input configurations there are several ways to drive the ad9653 either actively or passively. however, optimum performance is achieved by driving the analog input s differentially. using a d ifferential double balun configuration t o drive the ad9653 provides excellent perfor mance and a flexible interface to the adc (see figure 56 ) for baseband applications. for applications where snr is a key parameter, differential trans - former coupling is the recommended input configuration (see figure 57) , because the noise performance of most amplifiers is not adequate to achieve the true performance of the ad9653 . regardless of the configuration, the value of the shunt capacitor, c, is dependent on the input frequency and may need to be reduced or removed. it is not recommen ded to drive the ad9653 input s single - ended. voltage reference a stable and accurate voltage reference is built into the ad9653 . vref can be configured using either the internal 1.0 v refer - ence , an externally applied 1.0 v to 1.3 v reference voltage , or using an external resistor divider applied to the internal refer - ence to prod uce a reference voltage of the users choice . the various reference modes are summarized in the internal reference connection section and the external reference operation s ection. the vref pin should be externally bypassed to ground with a low esr, 1.0 f capacitor in parallel with a low esr, 0.1 f ceramic capacitor. internal reference connection a comparator within the ad9653 detects the potential at the sense pin and configures the reference into one of t hree possible modes, which are summarized in table 11 . if sense is grounded, the reference amplifier switch is connected to the internal resistor divider (see figure 54 ), setting the voltage at the vref pin, v ref , to 1.0 v. if sense is connected to an external resistor divider (see figure 55 ), v ref is defined as ? ? ? ? ? ? + = r1 r2 v ref 1 5 . 0 where: 7 k? ( r1 + r2 ) 10 k? figure 54 . 1.0 v internal reference configuration figure 55 . programmable internal referen ce configuratio n table 11 . reference configuration summary selected mode sense voltage (v) resulting v ref (v) resulting differential span (v p - p) fixed internal reference agnd to 0.2 1.0 internal 2.0 programmable internal refere nce tie to external r - divider (see figure 55) 0.5 (1 + r2/r1) , example: r1 = 3.5 k , r2 = 5.6 k for v ref = 1.3 v 1 2 v ref fixed external reference avdd 1.0 to 1.3 applied to external vref pin 1 2.0 to 2.6 1 normal operation for v ref = 1.3 v is supported over the 0 c to 85 c temperature range. 20 30 40 50 60 70 80 90 100 1 10 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 snr/sfdr (dbfs/dbc) common-mode vo lt age (v) sf dr (dbc) s n rf s (dbfs) 10538-053 vref sense 0.5v ad9653 select logic 0.1f 1.0f vin?a vin+a adc core 10538-054 vref sense r1 r2 0.5v ad9653 select logic 0.1f 1.0f vin?a vin+a adc core 10538-055 +
ad9653 data sheet rev. 0 | page 24 of 40 figure 56 . differential double balun input configurat ion for baseband applications figure 57 . differential transformer - coupled configuration for baseband applications if the internal reference of the ad9653 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. figure 58 and fi gure 59 show how the internal reference voltage is affected by loading. figure 58 . v ref = 1.0 v error vs. load current figure 59 . v ref =1.3 v error vs. load current external reference operation the use of an external reference may be necessary to enhance the gain accuracy of the adc or improve thermal drift charac - teristics. figure 60 and figure 61 show the typical dr ift characteris - tics of the internal reference in 1.0 v mode and programmable 1.3 v mode , respectively . adc r 0.1f 0.1f 2v p-p vcm c *c1 *c1 c r 0.1f 0.1f 0.1f 33? 200? 33? 33? 33? vin+x vin?x et1-1-i3 c c 5pf r *c1 is optional 10538-056 2v p-p r r *c1 *c1 is optional 49.9 0.1f adt1-1wt 1:1 z ratio vin?x adc vin+x *c1 c vcm 33? 33? 200? 0.1f 5pf 10538-057 0 ?0.5 ?1.0 ?1.5 ?2.0 ?2.5 ?3.0 ?3.5 ?4.0 ?4.5 ?5.0 0 3.0 2.5 2.0 1.5 1.0 0.5 v ref error (%) load current (ma) interna l v ref = 1.0v 10538-058 0 ?1 ?2 ?3 ?4 ?5 ?6 ?7 ?8 ?9 0 3.0 2.5 2.0 1.5 1.0 0.5 v ref error (%) load current (ma) interna l v ref = 1.3v 10538-059
data sheet ad9653 rev. 0 | page 25 of 40 figure 60 . typical v ref = 1.0 v drift figure 61 . typical v ref = 1.3 v drift when the sense pin is tied to avdd, the internal reference is disabled, allowing the use of an external reference. an internal reference buffer loads the external reference with an equivalent 7 .5 k? load (see figure 50 ). the internal buffer generates the positive and negative full - scale references for the adc core. it is not recommended to leave the sense pin floating. clock input consider ations for opti mum performance, clock the ad9653 sample clock inputs, clk+ and clk?, with a differential signal. the signal is typically ac - coupled into the clk+ and clk? pins via a transformer or capacitors. these pins are biased internally (see figure 44 ) and require no external bias. clock input options th e ad9653 has a flexible clock input structure. the clock in put can be a cmos, lvds, lvpecl, or sine wave signal. regard - less of the type of signal being used, clock source jitter is of the most concern, as described in the jitter considerations section. figure 62 and figure 63 show two preferred methods for clock - ing the ad9653 (at clock rates up to 1 ghz prior to internal clock divider). a low jitter clock source is converted from a single - ended signal to a differential signal using either an rf transformer or an rf balun. the rf balun configuration is recommended for clock fr equencies between 125 mhz and 1 ghz, and the rf transformer is recom - men ded for clock frequencies from 2 0 mhz to 200 mhz. the back - to - back schottky diodes across the transformer/balun secondary winding limit clock excursions into the ad9653 to approximately 0.8 v p - p differential. this limit helps prevent the large voltage swings of the clock from feeding through to other portions of the ad9653 while preserving the fast rise and fall times of the signal that are critical to a chieving low jitter performance. however, the diode capaci - tance comes into play at frequencies above 500 m hz. care must be taken in choosing the appropriate signal limiting diode. figure 62 . transformer - coupled differential clock (up to 200 mhz) figure 63 . balun - coupled differential clock (up to 1 ghz) if a low jitter clock source is not available, another option is to ac couple a differential pecl signal to the sample clock input pins, as shown in figure 64 . the ad9510/ ad9511 / ad9512 / ad9513 / ad9514 / a d9515 / ad9516 / ad9517 clock drivers offer excellent jitter performance. a third option is to ac couple a differential lvds signal to the sample clock input pins, as sh own in figure 65 . the ad9510/ ad9511 / ad9512 / ad9513 / ad9514 / ad9515 / ad9516 / ad9517 clock drivers offer excellent jitter performance. in some applications, it may be acceptable to drive the sample clock inputs with a single - ended 1.8 v cmos signal. in such applica tions, drive the clk+ pin directly from a cmos gate, and bypass the clk? pin to ground with a 0.1 f capa citor (see figure 66 ). figure 64 . differential pecl sample clock (up to 1 ghz) 4 ?8 ?40 85 v ref error (mv) temperature (c) ?6 ?4 ?2 0 2 ?15 10 35 60 10538-060 ?15 ?10 ?5 0 5 10 ?40 ?20 0 20 40 60 80 v ref error (mv) temper a ture (c) 10538-061 0.1f 0.1f 0.1f 0.1f schottky diodes: hsms2822 clock input 50? 100? clk? clk+ adc mini-circuits ? adt1-1wt, 1:1 z xfmr 10538-062 0.1f 0.1f 0.1f clock input 0.1f 50? clk? clk+ schottky diodes: hsms2822 adc 10538-063 10 0? 0.1f 0.1f 0.1f 0.1f 240? 240? 50k? 50k? clk? clk+ clock input clock input adc ad951x pecl driver 10538-064
ad9653 data sheet rev. 0 | page 26 of 40 figure 65 . differential lvds sample clock (up to 1 ghz) figure 66 . single - ended 1.8 v cmos input clock (up to 200 mhz) input clock divider the ad9653 contains an input clock divider with the ability to divide the inp ut clock by integer values between 1 and 8 . the ad9653 clock divider can be synchronized using the external sync input. bit 0 and bit 1 of register 0x109 allow the cl ock divider to be resynchronized on every sync signal or only on the first sync signal after the register is written. a valid sync causes the clock divider to reset to its initial state. this synchronization feature allows multiple parts to have their cloc k dividers aligned to guarantee simultaneous input sampling . clock duty cycle typical high speed adcs use both clock edges to generate a vari - ety of internal timing signals and, as a result, may be sensitive to clock duty cycle. commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. the ad9653 contains a duty cycle stabilizer (dcs) that retimes the nonsampling ( falling) edge, providing an internal clock signal with a nominal 50% duty cycle. this feature minimizes performance degradation in cases where the clock input duty cycle deviates from 50% greater than the specified 5% . noise and distortion perform ance are nearly flat for a wide r range of duty cycles with the dcs on, as shown in figure 67 and figure 68. figure 67 . snr vs. dcs on/off , v ref = 1.0 v figure 68 . snr vs. dcs on/off , v ref = 1. 3 v jitter in the rising edge of the input is still of concern and is not easily reduced by the internal stabilization circuit. the duty cycle control loop does not function for clock rates less than 20 mhz, nominally. the loop has a time constant associated with it that must be considered in applications in which the clock rate can change dynamically. a wait time of 1.5 s to 5 s is required after a dynamic clock frequency increase or decr ease before the dcs loop is relocked to the input signal. jitter considerations high speed, high resolution adcs are sensitive to the quality of the clock input. the degradation in snr at a given input frequency ( f a ) due only to aperture jitter ( t j ) can b e calculated by snr degradation = 20 log 10 ? ? ? ? ? ? ? ? j a t f 2 1 in this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and adc aperture jitter specifications. if und ersampling applications are particularly sensitive to jitter (see figure 69). the clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the ad9653 . power supplies for clock drivers should be separated from the 10 ? 0.1f 0.1f 0.1f 0.1f n? n? clk? clk+ adc clock input clock input ad951x lvds driver 10538-065 optional ? 0.1f 0.1f 0.1f ? 1 1 ?5(6,6725,6237,21$/ clk? clk+ adc v cc n? n? clock input ad951x cmos driver 10538-066 84 70 40 60 55 50 45 snr (dbfs) duty cycle (%) 10538-076 72 74 76 78 80 82 snrfs (dcs off) snrfs (dcs on) 84 70 40 60 55 50 45 snr (dbfs) duty cycle (%) 10538-077 72 74 76 78 80 82 snrfs (dcs off) snrfs (dcs on)
data sheet ad9653 rev. 0 | page 27 of 40 adc output driver supplies to avoid modulating the clock signal with digital noise. low jitter, crystal-controlled oscillators make the best clock sources. if the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step. refer to the an-501 application note and the an-756 application note for more in-depth information about jitter performance as it relates to adcs. figure 69. ideal snr vs. input frequency and jitter power dissipation an d power-down mode as shown in figure 70, the power dissipated by the ad9653 is proportional to its sample rate. the digital power dissipation does not vary significantly because it is determined primarily by the drvdd supply and bias current of the lvds output drivers. figure 70. analog core power vs. f sample for f in = 9.7 mhz, four channels the ad9653 is placed in power-down mode either by the spi port or by asserting the pdwn pin high. in this state, the adc typically dissipates 2 mw. during power-down, the output drivers are placed in a high impedance state. asserting the pdwn pin low returns the ad9653 to its normal operating mode. note that pdwn is referenced to the digital output driver supply (drvdd) and should not exceed that supply voltage. low power dissipation in power-down mode is achieved by shutting down the reference, reference buffer, biasing networks, and clock. internal capacitors are discharged when entering power-down mode and then must be recharged when returning to normal operation. as a result, wake-up time is related to the time spent in power-down mode, and shorter power-down cycles result in proportionally shorter wake-up times. when using the spi port interface, the user can place the adc in power-down mode or standby mode. standby mode allows the user to keep the internal reference circuitry powered when faster wake-up times are required. see the memory map section for more details on using these features. digital outputs and timing the ad9653 differential outputs conform to the ansi-644 lvds standard on default power-up. this can be changed to a low power, reduced signal option (similar to the ieee 1596.3 standard) via the spi. the lvds driver current is derived on chip and sets the output current at each output equal to a nominal 3.5 ma. a 100 differential termination resistor placed at the lvds receiver inputs results in a nominal 350 mv swing (or 700 mv p-p differential) at the receiver. when operating in reduced range mode, the output current is reduced to 2 ma. this results in a 200 mv swing (or 400 mv p-p differential) across a 100 termination at the receiver. the ad9653 lvds outputs facilitate interfacing with lvds receivers in custom asics and fpgas for superior switching performance in noisy environments. single point-to-point net topologies are recommended with a 100 termination resistor placed as close to the receiver as possible. if there is no far-end receiver termination or there is poor differential trace routing, timing errors may result. to avoid such timing errors, it is recommended that the trace length be less than 24 inches and that the differential output traces be close together and at equal lengths. an example of the fco and data stream with proper trace length and position is shown in figure 71. figure 72 shows the lvds output timing example in reduced range mode. figure 71. lvds output timing example in ansi-644 mode (default) 1 10 100 1000 16 bits 14 bits 12 bits 30 40 50 60 70 80 90 100 110 120 130 0.125ps 0.25ps 0.5ps 1.0ps 2.0ps analog input frequency (mhz) 10 bits 8 bits rms clock jitter requirement snr (db) 10538-067 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 20 40 60 80 100 120 analog core power (w) sample rate (msps) v ref =1.3v v ref =1.0v 10538-068 10538-069 d0 500mv/div d1 500mv/div dco 500mv/div fco 500mv/div 4ns/div
ad9653 data sheet rev. 0 | page 28 of 40 figure 72. lvds output timing example in reduced range mode an example of the lvds output using the ansi-644 standard (default) data eye and a time interval error (tie) jitter histo- gram with trace lengths less than 24 inches on standard fr-4 material is shown in figure 73. figure 73. data eye for lvds outputs in ansi-644 mode with trace lengths less than 24 inches on standard fr-4 material, external 100 far-end termination only figure 74. data eye for lvds outputs in ansi-644 mode with trace lengths greater than 24 inches on standard fr-4 material, external 100 far-end termination only figure 74 shows an example of trace lengths exceeding 24 inches on standard fr-4 material. notice that the tie jitter histogram reflects the decrease of the data eye opening as the edge deviates from the ideal position. it is the users responsibility to determine if the waveforms meet the timing budget of the design when the trace lengths exceed 24 inches. additional spi options allow the user to further increase the internal termination (increasing the current) of all four outputs to drive longer trace lengths. this can be achieved by programming register 0x15. even though this produces sharper rise and fall times on the data edges and is less prone to bit errors, the power dissipation of the drvdd supply increases when this option is used. the format of the output data is twos complement by default. an example of the output coding format can be found in table 12. to change the output data format to offset binary, see the memory map section. data from each adc is serialized and provided on a separate channel in two lanes in ddr mode. the data rate for each serial stream is equal to 16 bits times the sample clock rate, with a maximum of 500 mbps/lane [(16 bits 125 msps)/(2 2) = 500 mbps/lane]. the lowest typical conversion rate is 20 msps. see the memory map section for details on enabling this feature. d0 400mv/div d1 400mv/div dco 400mv/div fco 400mv/div 4ns/div 10538-070 6k 7k 1k 2k 3k 5k 4k 0 200ps 250ps 300ps 350ps 400ps 450ps 500ps tie jitter histogram (hits) 500 400 300 200 100 ?500 ?400 ?300 ?200 ?100 0 ?0.8ns ?0.4ns 0ns 0.4ns 0.8ns eye diagram voltage (mv) eye: all bits uls: 7000/400354 10538-071 500 400 300 200 100 ?500 ?400 ?300 ?200 ?100 0 ?0.8ns ?0.4ns 0ns 0.4ns ?0.8ns eye diagram voltage (mv) eye: all bits uls: 8000/414024 10k 12k 2k 4k 6k 8k 0k ?800ps ?600ps ?400ps ?200ps 0ps 200ps 400ps 600ps tie jitter histogram (hits) 10538-072
data sheet ad9653 rev. 0 | page 29 of 40 two output clocks are provided to assist in capturing data from the ad9653 . the dco is used to clock the output data and is equal to four times the sample clock (clk) rate for the default mode of operation . data is clocked out of the ad9653 and must be captu red on the rising and falling edges of the dco that supports double data rate (ddr) capturing. the fco is used to signal the start of a new output byte and is equal to the sample clock rate in 1 frame mode . see the timing diagrams section for more information. when the spi is used, the dco phase can be adjusted in 60 increments relative to the data edge. this enables the user to refine system timing margins if required. the default dco+ and dco? timing, as shown i n figure 2 , is 90 relative to the output data edge. in default mode, as shown in figure 2 , the msb is first in the data output serial stream. this can be inverted so that the lsb is first in the data output serial stream by using the spi. there are 12 digital output test pattern options available that can be initiated through the spi. this is a useful feature when validating receiver capture and timing. refer to table 13 for the output bit sequencing options available. some test patterns have two serial sequential words and can be alternated in various ways, depending on the test pattern chosen. note that some patterns do not adhe re to the data format select option. in addition, custom user - defined test patterns can be assigned in the 0x19, 0x1a, 0x1b, and 0x1c register addresses. table 12 . digital output coding input (v) condition (v) offset binary outp ut mode twos complement mode vin+ ? vin? < ? vref ? 0.5 lsb 0000 0000 0000 0000 1000 0000 0000 0000 vin+ ? vin? ? vref 0000 0000 0000 0000 1000 0000 0000 0000 vin+ ? vin? 0 v 1 00 0 0000 0000 0000 0000 0000 0000 0000 vin+ ? vin? +vref ? 1.0 lsb 1 111 1111 1111 11 11 01 11 1111 1111 11 11 vin+ ? vin? >+vref ? 0.5 lsb 11 11 1111 1111 11 11 0111 1111 1111 11 11 table 13 . flexible output test modes output test mode bit sequence pattern name digital output word 1 digital output word 2 subject to data format s elect notes 0000 off (default) n/a n/a n/a 0001 midscale short 10 00 0000 0000 0000 (1 6 - bit) n/a yes offset binary code shown 0010 +full - scale short 0000 0000 0000 0000 (1 6 - bit) n/a yes offset binary code shown 0011 ? full - scale short 0000 0000 0000 000 0 (16 - bit) n/a yes offset binary code shown 0100 checkerboard 1010 1010 1010 1010 (16 - bit) 0101 0101 0101 010 0 (1 6 - bit) no 0101 pn sequence long n/a n/a yes pn 23 itu 0 . 150 x 23 + x 18 + 1 0110 pn sequence short n/a n/a yes pn 9 itu 0 . 150 x 9 + x 5 + 1 0111 one - /zero - word toggle 11 1 1111 1111 1100 ( 16 - bit) 0000 0000 0000 0000 (1 6 - bit) no 1000 user input register 0 x 19 to register 0 x 1 a register 0 x 1 b to register 0 x 1 c no 1001 1 - / 0 - bit toggle 1010 1010 1010 10 0 0 ( 16- bit) n/a no 1010 1 sync 00 00 000 1 111 1 1 1 00 ( 16 - bit) n/a no 1011 one bit high 1000 0000 0000 0000 ( 16- bit) n/a no pattern associated with the external pin 1100 mixed frequency 10 10 000 1 1001 1100 (1 6 - bit) n/a no
ad9653 data sheet rev. 0 | page 30 of 40 the pn sequence short pattern produces a pseudorandom bit sequence that repeats itself every 2 9 ? 1 or 511 bits. a descrip - tion of the pn sequence and how it is generated can be found in section 5.1 of the itu - t 0.150 (05/96) standard. the seed value is all 1s (see table 14 for the initial values). the out put is a parallel representation of the serial pn9 sequence in msb - first format. the first output word is the first 14 bits of the pn9 sequence in msb aligned form. the pn sequence long pattern produces a pseudorandom bit sequence that repeats itself every 2 23 ? 1 or 8,388,607 bits. a description of the pn sequence and how it is generated can be found in section 5.6 of the itu - t 0.150 (05/96) standard. the seed value is all 1s (see table 14 for the initial values) and the ad9653 inverts the bit stream with relation to the itu standard. the output is a parallel representation of the serial pn23 sequence in msb - first format. the fir st output word is the first 14 bits of the pn23 sequence in msb aligned form table 14 . pn sequence sequence initial value first three output samples (msb first) twos comple ment pn sequence short 0x1fe0 0x1df1, 0x3cc8, 0x294e p n sequence long 0x1fff 0x1fe0, 0x2001, 0x1c00 consult the memory map section for information on how to change these additional digital output timing features through the spi. sdio/o l m pin for applications that do not require spi mode operation, the csb pin is tied to avdd , and the sdio/olm pin controls the o utput l ane m ode according to table 15. note that , when the csb pin is tied to avdd, the ad9653 dcs is on by default and remain s on unless the part is placed in spi mode and controlled via the spi . refer to the clock duty cycle section for more information on the dcs. for applications w here the sdio/olm pin is not used, csb sh ould be tied to avdd. when using the one - lane mode, the conversion rate should be 62.5 msps to meet the maximum output rate of 1 gbps. table 15 . output lane mode pin settings olm pin voltage output mode avdd (default) two -l ane. 1 frame , 16 -b it s erial o utput gnd one -l ane. 1 f rame, 16- bit seria l output sclk/dtp pin the sclk/dtp pin is used to select the digital test p attern (dtp) for applications that do not require spi mode operation. this pin can enable a single digital test pattern if it and the csb pin are held high during device power - up. when sclk/dtp is tied to avdd, the adc channel outputs shift out the following pattern: 1000 0000 0000 0000 . the fco and dco function normally while all channels shift out the repeatable test pattern. this pattern allows the user to perform timing alignmen t adjustments among the fco, dco, and output data. this pin has an internal 10 k? resistor to gnd. it can be left unconnected. table 16 . digital test pattern pin settings selected dtp dtp voltage resulting d0x and d1x normal ope ration 10 k to agnd normal operation dtp avdd 1000 0000 0000 0000 additional and custom test patterns can also be observed when commanded from the spi port. consult the memory map section for information about t he options available. csb pin the csb pin should be tied to avdd for applications that do not require spi mode operation. by tying csb high, all sclk and sdio information is ignored. note that, when the csb pin is tied to avdd, the ad9653 dcs is on by default and remains on unless the part is placed in spi mode and controlled via the spi. refer to the clock duty cycle section for more information on the dcs. rbias pin to set the internal core bias current of the adc, place a 10.0 k ?, 1% tolerance resistor to ground at the rbias pin. output test modes the output test options are described in table 13 and controlled by the output t est mode bits at address 0x0d. when an output test mode is enabled, the analog section of the adc is disconnected from the digital back - end blocks and the test pattern is run through the output formatting block. some of the test patterns are subject to out put formatting, and some are not. the pn generators from the pn sequence tests can be reset by setting bit 4 or bit 5 of register 0x0d. these tests can be performed with or without an analog signal (if present, the analog signal is ignored), but they do re quire an encode clock. for more information, see the an - 877 application note , interfacing to high speed adcs via spi .
data sheet ad9653 rev. 0 | page 31 of 40 serial port interface (spi) the ad9653 serial port interface (spi) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the adc. the spi offers the user added flexibility and customization, depending on the application. addresses are accessed via the serial port and can be written to or read from via the port. memory is organized into bytes that can be further divided into fields, which are docu- mented in the memory map section. for detailed operational information, see the an-877 application note , interfacing to high speed adcs via spi . configuration using the spi three pins define the spi of this adc: the sclk pin, the sdio pin, and the csb pin (see table 17). the sclk (a serial clock) is used to synchronize the read and write data presented from and to the adc. the sdio (serial data input/output) is a dual- purpose pin that allows data to be sent to and read from the internal adc memory map registers. the csb (chip select bar) is an active low control that enables or disables the read and write cycles. table 17. serial port interface pins pin function sclk serial clock. the serial shift clock input, which is used to synchronize serial interface reads and writes. sdio serial data inp ut/output. a dual-purpose pin that typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. csb chip select bar. an active low control that gates the read and write cycles. the falling edge of the csb, in conjunction with the rising edge of the sclk, determines the start of the framing. an example of the serial timing and its definitions can be found in figure 75 and table 7. other modes involving the csb are available. the csb can be held low indefinitely, which permanently enables the device; this is called streaming. the csb can stall high between bytes to allow for additional external timing. when csb is tied high, spi functions are placed in high impedance mode. this mode turns on any spi pin secondary functions. during an instruction phase, a 16-bit instruction is transmitted. data follows the instruction phase, and its length is determined by the w0 and w1 bits. in addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on-chip memory. the first bit of the first byte in a multibyte serial data transfer frame indicates whether a read command or a write command is issued. if the instruction is a readback operation, performing a readback causes the serial data input/output (sdio) pin to change direction from an input to an output at the appropriate point in the serial frame. all data is composed of 8-bit words. data can be sent in msb- first mode or in lsb-first mode. msb-first mode is the default on power-up and can be changed via the spi port configuration register. for more information about this and other features, see the an-877 application note , interfacing to high speed adcs via spi . figure 75. serial port interface timing diagram don?t care don?t care don?t care don?t care sdio sclk csb t s t dh t clk t ds t h r/w w1 w0 a12 a11 a10 a9 a8 a7 d5 d4 d3 d2 d1 d0 t low t high 10538-073
ad9653 data sheet rev. 0 | page 32 of 40 hardware interface the pins described in tab le 17 comprise the physical interface between the user programming device and the serial port of the ad9653 . the sclk pin and the csb pin function as inputs when usi ng the spi interface. the sdio pin is bidirectional, functioning as an input during write phases and as an output during readback. the spi interface is flexible enough to be controlled by either fpgas or microcontrollers. one method for spi configuration is described in detail in the an - 812 application note , micro - controller - based serial port interface (spi) boot circuit . the spi port should not be active during periods when the full dynamic performance of the converter is required. because the sclk signal, the csb signal, and the sdio signal are typically asynchronous to the adc clock, noise from these signals can degrade converter performance. if the on - board spi bus is used for other devices, it may be necess ary to provide buffers between this bus and the ad9653 to prevent these signals from transi - tioning at the converter inputs during critical sampling periods. some pin s serve a dual function when the spi interface is not being used. when the pins are strapped to drvdd or ground during device power - on, they are associated with a specific function. table 15 and table 16 describe the strappable functions supported on the ad9653 . configuration withou t the spi in applications that do not interface to the spi control registers, the sdio/o l m pin, the sclk/dtp pin, and the pdwn pin serve as standalone cmos - compatible control pins. when the device is powered up, it is assumed that the user intends to use the pins as static control lines for the output lane mod e , digital test pattern , and power - down feature control. in this mode, csb should be connected to avdd, which disables the serial port interface. note that, when the csb pin is tied to avdd, the ad9653 dcs is o n by default and remains on unless the part is placed in spi mode and controlled via the spi. refer to the clock duty cycle section for more information on the dcs. when the device is in spi mode, the pdwn pin (if enabled) remains active. for spi control of power - down, the pdwn pin should be set to its default state. spi accessible featu res table 18 provides a brief description of the general features that are accessible via the spi. these features are described in detail in the an - 877 application note , interfacing to high speed adcs via spi . the ad9653 part - specific features are described in detail following table 19 , the external memory map register table. table 18 . features accessible using the spi feature name description po wer mode allows the user to set either power - down mode or standby mode clock allows the user to set the clock divider, set the clock divider phase, and enable the sync offset allows the user to digitally adjust the converter offset test i/o allows the u ser to set test modes to have known data on output bits output mode allows the user to set the output mode output phase allows the user to set the output clock polarity
data sheet ad9653 rev. 0 | page 33 of 40 memory map reading the memory m ap register table each row in the memory map re gister table has eight bit locations . the memory map is roughly divided into three sections: the chip configuration registers (address 0x00 to address 0x02); the device index and transfer registers (address 0x05 and address 0xff) ; and the global adc functi ons registers, including setup, control, and tes t (address 0x08 to address 0x109 ) . the memory map register table ( see table 19 ) lists the default hexadecimal value for each hexadecimal address shown. the column wit h the heading bit 7 (msb) is the start of the default hexadecimal value given. for example, address 0x05, the device i ndex register, has a hexadecimal default value of 0x3f . this means that in address 0x05 , bit s [7: 6] = 0, and the remaining bits[5 :0] = 1 . t his setting is the default channel index setting. the default value results in both adc channels receiving the next write command. for more information on this function and others, see the an - 877 application note , interfacing to high speed adcs via spi. this application note details the functions controlled by register 0x00 to register 0xff. the remaining registers are documented in the memory map register descriptions se ction. open locations all address and bit locations that are not included i n table 19 are not currently supported for this device. unused bits of a valid address location should be written with 0s. writing to these locations is required only when part of an address location is open (for example, address 0x05). if the entire address location is open or not listed in table 19 (for example, address 0x13 ) , this address location should not be written. default values after the ad9653 is reset, critical registers are loaded with default values. the default values for the registers are given in the memory map register table, table 19. logic levels an explanation of logic level terminology follows: ? bit is set is synonymous with bit is set to logic 1 or writing logic 1 for the bit. ? clear a bit is synonymous with bit is set to logic 0 or writing logic 0 for the bit. channel - specific registers some channel setup functions, such as the signal monitor thresholds, can be programmed differently for each channel. in these cases, channel address locati ons are internally duplicated for each channel. these registers and bits are designated in table 19 as local. these local registers and bits can be accessed by setting the appropriate data channel bits (a, b, c, or d) and the clock channel dco bit (bit 5) and fco bit (bit 4) in register 0x05. if all the bits are set, the subsequent write affects the registers of all channels and the dco/fco clock channels. in a read cycle, only one of the channels ( a, b, c, or d ) sh ould be set to read one of the four registers. if all the bits are set during a spi read cycle, the part returns the value for channel a. registers and bits designated as global in table 19 affect the entire part o r the channel features for which independent settings are not allowed between channels. the settings in register 0 x 05 do not affect the global registers and bits.
ad9653 data sheet rev. 0 | page 34 of 40 m emory m ap r egister t able the ad9653 uses a 3 - wire interface and 16 - bit addressing and , therefore , bit 0 and bit 7 in register 0x00 are set to 0, and bit 3 and bit 4 are set to 1 . when bit 5 in register 0x00 is set high, the spi enter s a soft reset , where all of the user registers revert to their default values and bit 2 is automatically cleared. table 19. addr (hex) parameter name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) def ault value (hex) comments chip confi guration registers 0x00 spi port c onfiguration 0 = sdo active lsb f irst soft r eset 1 = 16 - bit address 1 = 16 - bit address soft r eset lsb f irst 0 = sdo active 0x18 the nibbles are mirrored so that lsb - first or msb - first mode register s correctly. the defau lt for adcs is 16 - bit mode. 0x01 chip id (global) 8 - b it c hip id , bits[ 7:0 ] ad9653 0x b5 = q uad , 1 6 - bit , 125 msps s er ial lvds 0x b5 unique chip id used to differentiate devices; read only. 0x02 chip grade (global) open speed grade id[6:4] 110 = 125 msps open open open open unique speed grade id used to differentiate graded devices ; r ead only. device index and transfer registers 0x05 device index open open clock ch annel dco clock channel fco data channel d data channel c data channel b data channel a 0x3f bits are set to determine which device on chip receives the next write command. the default is all devices on chip. 0xff transfer open open open open open open op en initiate o verride 0x00 set s ample r ate o verride . global adc function registers 0x08 power modes (global) open open external power - down pin function 0 = full power - down 1 = standby open open open power mode 00 = chip run 01 = full power - down 10 = stand by 11 = reset 0x00 determines various generic modes of chip operation. 0x09 clock (global) open open open open open open open duty cycle stabilize 0 = on 1 = o ff 0x01 turns duty cycle stabilizer on or off.
data sheet ad9653 rev. 0 | page 35 of 40 addr (hex) parameter name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) def ault value (hex) comments 0x0b clock d ivide (global) open open open open o pen clock divide ratio [2:0] 000 = divide by 1 001 = divide by 2 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8 0x00 0x0c enhancement control open open open open open chop mode 0 = off 1 = on open open 0x00 enables/ disables chop mode. 0x0d test m ode (local except for pn sequence resets) user i nput t est m ode 00 = single 01 = alternate 10 = single once 11 = alternate once (a ffects user input test mode only , bits[3:0] = 1000 ) reset pn l ong g en re set pn s hort g en output test mode [3:0] (local) 0000 = off (default) 0001 = midscale short 0010 = positive fs 0011 = negative fs 0100 = alternating checkerboard 0101 = pn 23 sequence 0110 = pn 9 sequence 0111 = one/zero word toggle 1000 = user input 1001 = 1 - /0 - bit toggle 1010 = 1 sync 1011 = one bit high 1100 = mixed bit frequency 0x00 when set, the test data is placed on the output pins in place of normal data . 0x10 offset a djust (local) 8 - bit device offset adjustment [7:0] (local) offset adjust in lsb s from +127 to ?128 (twos complement format) 0x00 device offset trim . 0x14 output mode open lvds - ansi/ lvds - ieee option 0 = lvds - ansi 1 = lvds - ieee reduced range link (global) see table 20 open open open output invert (local) open output format 0 = offset binary 1 = twos comple - ment (global) 0x 0 1 configures the outputs and the format of the data. 0x15 output adjust open open output driver termination [1:0] 00 = none 01 = 200 10 = 100 11 = 100 open open ope n output drive 0 = 1 drive 1 = 2 drive 0x00 determines lvds or other output properties. 0x16 output phase open input clock phase adjust[6:4] (value is number of input clock cycles of phase delay) see table 21 o utput clock phase adjust[3:0] (0000 through 1011) see table 22 0x03 on devices that use global clock divide, determines which phase of the divider output is used to supply the output clock. internal latching is una ffected.
ad9653 data sheet rev. 0 | page 36 of 40 addr (hex) parameter name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) def ault value (hex) comments 0x18 v ref open open open open open v ref adjustment digital scheme [2:0] 000 = 1.0 v p - p (1.3 v p - p) 001 = 1.14 v p - p (1.48 v p - p) 010 = 1.33 v p - p (1.73 v p - p) 011 = 1.6 v p - p (2.08 v p - p) 100 = 2.0 v p - p (2.6 v p - p) 0x04 select s internal v ref . va lues shown are for v ref = 1.0 v (1.3 v) . 0x19 user_patt1_lsb (global) b7 b6 b5 b4 b3 b2 b1 b0 0x00 user defined pattern 1 lsb. 0x1a user_patt1_msb (global) b15 b14 b13 b12 b11 b10 b9 b8 0x00 user defined pattern 1 msb. 0x1b user_patt2_lsb (global) b7 b6 b5 b4 b3 b2 b1 b0 0x00 user defined pattern 2 lsb. 0x1c user_patt2_msb (global) b15 b14 b13 b12 b11 b10 b9 b8 0x00 user defined pattern 2 msb. 0x21 serial output data control (global) lvds output lsb first sdr/ddr one - lane/ two - lane, bit wise/ byte wise[6: 4] 000 = sdr two - lane, bit wise 001 = sdr two - lane, bytewise 010 = ddr two - lane, bit wise 011 = ddr two - lane, bytewise 100 = ddr one - lane , wordwise open select 2 frame serial output number of bits 00 = 16 bits 0x30 serial stream control. default causes ms b first and the native bit stream. 0x22 serial channel s tatus (local) open open open open open open channel output reset channel power - down 0x00 used to power down individual sections of a converter. 0x100 sample rate override open sample rate override e nable 0 0 open sample rate 000 = 20 msps 001 = 40 msps 010 = 50 msps 011 = 65 msps 100 = 80 msps 101 = 105 msps 110 = 125 msps 0x00 sample rate override (requires transfer register, 0xff). 0x101 user i/o control 2 open open open open open open open sdio pull - down 0x 00 disables sdio pull - down. 0x102 user i/o control 3 open open open open vcm power - down open open open 0x00 vcm control. 0x109 sync open open open open open open sync next only enable sync 0x00
data sheet ad9653 rev. 0 | page 37 of 40 memory map register descriptions for a dditional information about functions controlled in register 0x00 to register 0xff, see the an - 877 application note , interfacing to high speed adcs via spi . device index (register 0x05) there are certain featur es in the map that can be set inde - pendently for each channel, whereas other features apply globally to all channels (depending on context) regardless of which are selected. the first four bits in register 0x05 can be used to select which individual data c hannels are affected. the output clock channels can be selected in register 0x05 as well. a smaller subset of the independent feature list can be applied to those devices. transfer (register 0xff) all registers except register 0x100 are updated the momen t they are written. setting bit 0 of this transfer register high initializes the settings in the sample rate override register (address 0 x 100). power modes (register 0x08) bits[ 7:6 ] open bit 5 external power - down pin function if set, the external pdwn pin initiates standby mode. if clear ed , the external pdwn pin initiates power - down mode. bits[ 4:2 ] open bits[1:0] power mode in normal operation (bits[ 1:0 ] = 00 ), all adc channels are active. in power - down mode (bits[1:0] = 01), the digital datapath clocks are disabled while the digital datapath is reset. outputs are disabled . in standby mode (bits[1:0] = 10), the digital datapath clocks and the outputs are disabled. during a digital reset (bits[1:0] = 11), all the digital datapath clocks and the outputs (where applicable) on the chip are reset , except the spi port. note that the spi is always left under control of the user; that is, it is never automatically disabled or in reset (except by power - on reset). clock (register 0x09) bits[ 7:1 ] open bit 0 duty cycle s tabilize. the d efault state is bit 0 = 1 , duty cycle stabilizer off. note that , when the part is not in spi mode, the duty cycle stabilizer is on. refer to the configuration without the spi section for more informa tion. enhancement control (register 0x0c) bits[ 7:3 ] open bit 2 chop mode for applications that are sensitive to offset voltages and other low frequency noise, such as homodyne or direct conversion receivers, chopping in the first stage of the ad9653 is a feature that can be enabled by setting bit 2. in the frequency domain, chopping translates offsets and other low frequency noise to f clk / 2 where it can be filtered. bi ts[ 1:0 ] open output mode (register 0x14) bit 7 open bit 6 lvds - ansi/lvds - ieee option setting this bit chooses lvds - ieee (reduced range) option. the default setting is lvds - ansi. as described in table 20, when lvds - ansi or lvds - ieee reduced range link is selected, the user can select the driver termination. the driver current is automatically selected to give the proper output swing. table 20 . lvds - ansi/lvds - ieee options output mode, bit 6 output mode output driver termination output driver current 0 lvds - ansi user selectable automatically selected to give proper swing 1 lvds -ieee reduced range link user selectable automatically selected to give proper swing bits[ 5:3 ] open bit 2 output in vert setting this bit inverts the output bit stream. bit 1 open bit 0 output format by default, this bit is set to send the data output in twos complement format. resetting this bit changes the output mode to offset binary. output adjust (register 0x15) bi ts[ 7:6 ] open bits[5:4] output driver termination these bits allow the user to select the internal termination resistor. bits[ 3:1 ] open bit 0 output drive bit 0 of the output adjust register controls the drive strength on the lvds driver of the fco and dco outputs only. the default values set the drive to 1 while the drive can be increased to 2 by setting the appropriate channel bit in register 0x05 and then setting bit 0. these features cannot be used with the output driver termina tion select. the termi nation selection takes precedence over the 2 driver strength on fco and dco when both the output driver termination and output drive are selected.
ad9653 data sheet rev. 0 | page 38 of 40 output phase (register 0x16) bit 7 open bits[ 6:4 ] input clock phase adjust table 21. input clock phase adjust options input clock phase adjust , bits [ 6:4 ] number of input clock cycles of phase delay 000 (default) 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 bits[ 3:0 ] output clock phase adjust table 22 . outpu t clock phase adjust options output clock (dco), phase adjust , bits [ 3:0 ] dco phase adjustment (degrees relative to d 0 x/d 1 x edge) 0000 0 0001 60 0010 120 0011 (default) 180 0100 240 0101 300 0110 360 0111 420 1000 480 1001 540 1010 600 1011 660 serial output data control (register 0x21) the serial output data control register is used to program the ad9653 in various output data modes depending upon the d ata capture solution. table 23 describes the various serialization options available in the ad9653 . sample rate override (re gister 0x100) this register is designed to allow the user to downgrade the sample rate . settings in this register are not initialized until bit 0 of the transfer register (register 0 xff) is written high. user i/o control 2 (register 0x101) bits[ 7 : 1 ] open b it 0 sdio pull - down bit 0 can be set to disable the internal 30 k pull - down on the sdio pin, which can be used to limit the loading when many devices are connected to the spi bus. user i/o control 3 (register 0x102) bits[ 7:4 ] open bit 3 vcm power - down bit 3 can be set high t o power down the internal vcm generator. this feature is used when applying an external reference. bits[ 2:0 ] open table 23. spi register options serialization options selected register 0x21 contents serial output number of bits (sonb) frame mode serial data mode dco multiplier timing diagram 0x30 16- bit 1 ddr two - l ane , b yte wise 4 f s figure 2 (default setting) 0x20 16- bit 1 ddr two - l ane , b it wise 4 f s figure 2 0x10 16- bit 1 sdr two - l ane , bytewise 8 f s figure 2 0x00 16- bit 1 sdr two - l ane , bitwise 8 f s figure 2 0x34 16 - bit 2 ddr two - l ane , bytewise 4 f s figure 3 0x24 16- bit 2 ddr two - l ane , bitwise 4 f s figure 3 0x14 16- bit 2 sdr two - l ane , bytewise 8 f s figure 3 0x04 16 - bit 2 sdr two - l ane , bitwise 8 f s figure 3 0x40 16- bit 1 ddr one - l ane , wordwise 8 f s figure 4
data sheet ad9653 rev. 0 | page 39 of 40 a pplications information design guidelines before starting design an d layout of the ad9653 as a system, it is recommended that the designer become familiar with these guidelines, which describes the special circuit connections and la yout requirements that are needed for certain pins. power and ground rec ommendations when connecting power to the ad9653 , it is recommended that two separate 1.8 v su pplies be used. use one supply for analog (avdd); use a separate supply for the digital outputs (drvdd). for both avdd and drvdd , se veral different decoupling capa citors should be used to cover both high and low frequencies. place these capacitors close to the point of entry at the pcb level and close to the pins of the part, with minimal trace length. a single pcb ground plane should be sufficient when using the ad9653 . with proper decoupling and smart partitioning of the pcb analog, digital, and clock sections, optimum performance is easily achieved. exposed pad thermal heat slug recommendations it is required that the exposed pad on the underside of the adc be connec ted to analog ground (agnd) to achieve the best electrical and th ermal performance of the ad9653 . an exposed continuous copper plane on the pcb should mate to the ad9653 exposed pad, pin 0. the copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the botto m of the pcb. these vias should be solder - filled or plugged. to maximize the coverage and adhesion between the adc and pcb, partition the continuous copper plane by overlaying a silkscreen on the pcb into several uniform sections. this provides several tie points between the adc and pcb during the reflow process, whereas using one continuous plane with no partitions only guarantees one tie point. see figure 76 for a pcb layout example. for detailed information o n packaging and the pcb layout of chip scale packages, see the an - 772 application note , a design and manufacturing guide for the lead frame chip scale package (lfcsp) , at www .analog.com . figure 76 . typical pcb layout vcm the vcm pin should be bypassed to ground with a 0.1 f capacitor. reference decoupling the vref pin should be externally bypass ed to ground with a low esr, 1.0 f capacitor in parallel with a low esr, 0.1 f ceramic capacitor. spi port the spi port should not be active during periods when the full dynamic performance of the converter is required. because the sclk, csb, and sdio signals are typically asynchronous to the adc clock, noise from these signals can degrade converter performance. if the on - board spi bus is used for other devi ces, it may be necessary to provide buffers between this bus and the ad9653 to keep these signals from transitioning at the con - verter inputs during critical sampling periods. crosstalk performanc e the ad9653 is available in a 48 - lead lfcsp package with the input pairs on either corner of the chip. see figure 6 for the pin configuration. to maximize the crosstalk performance on the board, add grounded filled vias in between the adjacent channels as shown in figure 77. figure 77 . layout technique to maximize crosstalk performance silkscreen p artition pin 1 indic a t or 10538-074 grounded filled vias for added crosstalk isolation vin channel b vin channel c vin channel a vin channel d pin 1 10538-075
ad9653 data sheet rev. 0 | page 40 of 40 outline dimensions figure 78 . 48 - lead lead frame chip scale package [lfcsp_wq] 7 mm 7 mm body, very very thin quad (cp - 48 - 13) dimensions shown in millimeters orde ring guide model 1 temperature range package description package option ad9653 bcpz - 125 ? 40 c to + 85 c 48 - lead lead frame chip scale package (lfcsp_wq) cp -48 -13 ad9653 bcpzrl 7 - 125 ? 40 c to + 85 c 48 - lead lead frame chip scale package (lfcsp_wq) cp -48 -13 ad9653 -125 ebz evaluation board 1 z = rohs compliant part. compliant to jedec standards mo-220- wkkd . 1 0.50 bsc bot t om view top view pin 1 indic a t or 48 13 24 36 37 exposed pa d pin 1 indic a t or 5.65 5.60 sq 5.55 0.45 0.40 0.35 sea ting plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.23 0.18 02-14-20 1 1-b 7.10 7.00 sq 6.90 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.20 min ? 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10538 - 0 - 5/12(0)

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